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semiconductor group 12.99 target datasheet 3.3v sdram modules 144 pin so-dimm sdram modules pc100 & pc133 256mb density in cob technique HYS64V32220GCDL ? 144 pin eight byte small outline dual-in-line synchronous dram modules for notebook applications ? two bank 32m x 64 non-parity module organisation ? suitable for use in pc100 and pc133 applications ? performance: ? single +3.3v( 0.3v ) power supply ? programmable cas latency, burst length and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? decoupling capacitors mounted on substrate ? all inputs, outputs are lvttl compatible ? serial presence detect with e 2 prom ? uses cob (chip-on-board) technique ? 4096 refresh cycles every 64 ms ? gold contact pad ? this module family is fully pin and functional compatible with the latest intel so-dimm specification -7.5 -8 pc133 3-3-3 pc100 2-2-2 units f ck clock frequency (max.) 133 100 mhz t ac clock access time cas latency = 2 & 3 5.4 6 ns 17.99
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 2 12.99 target datasheet this infineon module is an industry standard 144 pin 8-byte synchronous dram (sdram) small outline dual in-line memory modules (so-dimm) which are organised as 32mx64 high speed memory arrays designed for use in non-parity applications. these so-dimms use cob (chip-on- board) technology. decoupling capacitors are mounted on the board. the dimms use optional serial presence detects implemented via a serial e 2 prom using the two pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 144-pin so-dimms provide a high performance, flexible 8-byte interface in a 67,5 mm long footprint. product spectrum: note: all partnumbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: HYS64V32220GCDL-8-c, indicating rev.c dies are used for sdram components. card dimensions: pin names sdrams used rowaddr. bank select column addr. refresh period 32m x 64 HYS64V32220GCDL-7.5 16 16mx8 12 ba0, ba1 10 4k 64 ms 32m x 64 hys64v322220gcdl-8 16 16mx8 12 ba0, ba1 10 4k 64 ms organisation pcb-board l x h x t [mm] 32m x 64 l-dim-144-cx 67.60 x tbd x 3.80 a0-a11 address inputs ba0,ba1 bank selects dq0 - dq63 data input/output ras row address strobe cas column address strobe we read / write input cke0 clock enable clk0 clock input dqmb0 - dqmb7 data mask cs0 - cs3 chip select vcc power (+3.3 volt) vss ground scl clock for presence detect sda serial data out for presence detect n.c. no connection
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 3 12.99 target datasheet pin configuration pin # front side pin # back side pin # front side pin # back side 1 vss 2 vss 73 nc 74 clk1 3dq0 4dq32 75vss 76vss 5dq1 6dq33 77nc 78nc 7dq2 8dq34 79nc 80nc 9 dq3 10 dq35 81 vcc 82 vcc 11 vcc 12 vcc 83 dq16 84 dq48 13dq4 14dq36 85dq17 86dq49 15dq5 16dq37 87dq18 88dq50 17dq6 18dq38 89dq19 90dq51 19 dq7 20 dq39 91 vss 92 vss 21 vss 22 vss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 vcc 28 vcc 99 dq23 100 dq55 29 a0 30 a3 101 vcc 102 vcc 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 vss 36 vss 107 vss 108 vss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 vcc 114 vcc 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 vcc 46 vcc 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 vss 120 vss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 vss 56 vss 127 dq27 128 dq59 57 nc 58 nc 129 vcc 130 vcc 59 nc 60 nc 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 vcc 64 vcc 135 dq30 136 dq62 65 ras 66 cas 137 dq31 138 dq63 67 we 68 cke1 139 vss 140 vss 69 cs0 70 (a12) 141 sda 142 scl 71 cs1 72 (a13) 143 vcc 144 vcc
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 4 12.99 target datasheet block diagram for two bank 32m x 64 sdram dimm - module dqm dq0-dq7 d0 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d1 cs1 cs0 dqmb0 dq(7:0) dqmb1 dq(15:8) dqmb2 dq(23:16) dqmb3 dq(31:24) a0-a11,ba0,ba1 vdd vss d0 - d7 c d0 - d7 d0 - d7 d0 - d15 d0 - d3 ras , cas , we cke0 dqm dq0-dq7 d4 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d5 dqm dq0-dq7 d2 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d3 dqmb4 dq(39:32) dqmb5 dq(47:40) dqmb6 dq(55:48) dqmb7 dq(63:56) dqm dq0-dq7 d6 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d7 d4 - d7 cke1 e 2 prom (256wordx8bit) scl sda sa0 sa1 sa2 note: 1. dq wiring may differ than describes in this drawing, however dq/dqmb/cke/cs relationship must be maintained as shown. 2. in this design each of the d0 - d7 components are represented by two 16m x 8 chips. these two chips effectively work as a single 16m x 16 device. 4 sdram clk0 clk1 4 sdram
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 5 12.99 target datasheet dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input high voltage v i h 2.0 vcc+0.3 v input low voltage v i l C 0.5 0.8 v output high voltage ( i out = C 4.0 ma) v oh 2.4 C v output low voltage ( i out = 4.0 ma) v ol C0.4v input leakage current, any input (0 v < v i n < 3.6 v, all other inputs = 0 v) i i (l) C 20 20 m a output leakage current (dq is disabled, 0 v < v out < v cc ) i o(l) C 20 20 m a parameter symbol limit values unit 16m x 64 max. input capacitance (a0 to a11, ba0, ba1) c i 1 65 pf input capacitance (ras , cas , we ) c i 2 75 pf input capacitance (clk0, clk1) c i 3 58 pf input capacitance (cs0, cs1) c i 4 40 pf input capacitance (dqmb0-dqmb7) c i 5 15 pf input capacitance (cke0, cke1) c i 6 50 pf input / output capacitance (dq0-dq63) c i o 18 pf input capacitance (scl,sa0-2) c sc 8pf input/output capacitance c sd 10 pf
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 6 12.99 target datasheet operating currents per memory bank (t a = 0 to 70 o c, vdd = 3.3v 0.3v (recommended operating conditions unless otherwise noted) notes: 1. these parameters depend on the cycle rate. these values are measured at 100 mhz operation frequency. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. parameter & test condition symb. 32mx64 256mbyte note operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 960 ma 1 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 12 ma 1 tck = infinity icc2ps 8ma1 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 280 ma 1 tck = infinity icc2ns 40 ma 1 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 360 ma 1 cke<=vil(max.) icc3p 64 ma 1 burst operating current tck = min., read command cycling icc4 960 ma 1,2 auto refresh current tck = min., auto refresh command cycling icc5 1360 ma 1 self refresh current self refresh mode, cke=0.2v icc6 6.4 ma 1
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 7 12.99 target datasheet ac characteristics 1)2) t a = 0 to 70 c; v ss = 0 v; vdd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 C C 10 10 C C ns ns clock frequency cas latency = 3 cas latency = 2 t ck C C 133 100 C C 100 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 ns ns 2, 3 clock high pulse width t ch 2.5 C 3 C ns clock low pulse width t cl 2.5 C 3 C ns transition time t t 0.3 1.2 0.5 10 ns setup and hold parameters input setup time t is 1.5 C 2 C ns 4 input hold time t ih 0.8 C 1 C ns 4 power down mode entry time t sb C1C1clk 4 power down mode exit setup time t pde 1C1Cclk 4 mode register set-up time t rsc 2C2Cclk common parameters row to column delay time t rcd 20C20Cns 5 row precharge time t rp 20C20Cns 5 row active time t ras 45 100k 50 100k ns 5 row cycle time t rc 67C70 C ns 5 activate(a) to activate(b) command period t rrd 14C16Cns 5 cas (a) to cas (b) command period t ccd 1C1Cclk
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 8 12.99 target datasheet refresh cycle refresh period (4096 cycles) t ref C64C64ms self refresh exit time t srex 1C1Cclk 6 read cycle data out hold time t oh 3C3Cns data out to low impedance time t lz 1C0Cns data out to high impedance time t hz 3738ns 7 dqm data out disable latency t dqz C2C2clk write cycle data input to precharge (write recovery) t wr 2C2Cclk dqm write mask latency t dqw 0C0Cclk parameter symbol limit values unit -7.5 pc133-333 -8 pc100-222 min. max. min. max.
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 9 12.99 target datasheet notes: 1. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown.specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v. 3. if clock rising time is longer than 1ns, a time (t t -0.5) ns has to be added to this parameter. 4. if t t is longer than 1ns, a time (t t -1) ns has to be added to this parameter. 5. any time that the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to wake-up the device. 6. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 50 pf i/o measurement conditions for tac and toh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 10 12.99 target datasheet serial presence detects: a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol ( i 2 c synchronous 2-wire bus) spd-table for pc100 2-2-2 so-dimm modules: byte# description spd entry value hex 32mx64 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs) 0c 4 number of column addresses 10 5 number of dimm banks 1 / 2 02 6 module data width 64 40 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns a0 10 sdram access time from clock at cl=3 6.0 ns 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s 80 1 3 s d r a m w i d t h , p r i m a r y x 1 6 1 0 14 error checking sdram data width n/a / x8 00 15 minimum clock delay for back-to- back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/ non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 sdram cycle time at cl = 2 10.0 ns a0 24 sdram access time from clock at cl=2 6.0 ns 60 25 sdram cycle time at cl = 1 not supported ff 26 sdram access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 11 12.99 target datasheet spd-table (contd): byte# description spd entry value hex 32mx64 -8 28 minimum row active to row active delay 16 ns 10 29 minimum ras to cas delay 20 ns 14 30 minimum ras pulse width 45 ns 2d 31 module bank density (per bank) 128 mb 20 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input setup time 2 ns 20 35 sdram data input hold time 1 ns 10 36-61 superset information ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 tbd 64- 125 manufacturess information (optional) ff 126 frequency specification pc100 64 127 details c7 128+ unused storage locations ff
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 12 12.99 target datasheet spd-table for pc133 3-3-3 so-dimm modules: byte# description spd entry value hex 32mx64 -7.5 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs) 0c 4 number of column addresses 10 5 number of dimm banks 1 / 2 02 6 module data width 64 40 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s 80 1 3 s d r a m w i d t h , p r i m a r y x 1 6 1 0 14 error checking sdram data width n/a / x8 00 15 minimum clock delay for back-to- back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/ non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 sdram cycle time at cl = 2 10.0 ns a0 24 sdram access time from clock at cl=2 6.0 ns 60 25 sdram cycle time at cl = 1 not supported ff 26 sdram access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 13 12.99 target datasheet spd-table (contd): byte# description spd entry value hex 32mx64 -7.5 28 minimum row active to row active delay 14 ns 0f 29 minimum ras to cas delay 20 ns 14 30 minimum ras pulse width 45 ns 2d 31 module bank density (per bank) 128 mb 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08 36-61 superset information ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 tbd 64- 125 manufacturess information (optional) ff 126 frequency specification pc133 85 127 details c7 128+ unused storage locations ff
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 14 12.99 target datasheet 256 mbyte so-dimm module package (preliminary !!) (144 pin, dual read-out, single in-line memory module) gld09192 67.6 63.6 25.4 3.3 23.2 3.8 1 0.1 20 3.7 detail of contacts min. 2.54 0.25 max. 0.6 0.05 0.8 1 1.8 4 6 59 61 143 32.8 2.5 4.6 2 60 62 144 1.5 0.1 0.1 4 24.5
HYS64V32220GCDL 144 pin so-dimm sdram modules infineon technologies 15 12.99 target datasheet
hy s 64v32220 gc dl 144 pin so-dimm sdram modules infineon technologies 16 12.99 target datasheet rev changes: 9.8.1999 first version 256mbyte cob-so-dimm based on 128 mb (16m x 8) chips 3.12.99 some pc133 timing parameters changed according to intels pc133 specifi- cation

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